1. Field of the Invention
The present invention relates to complementary metal oxide semiconductor (CMOS) devices, and more particularly to a process and structure for forming a metal oxide semiconductor field effect transistor (MOSFET), wherein gate sidewall composite spacers, which are partially removed during device processing, are employed. The present invention thus provides a method to form low temperature silicide contacts that are self-aligned to the deep junction edges present in the device, while still achieving the lower thermal budget of a conventional disposable spacer process.
2. Background of the Invention
As CMOS technology becomes smaller and smaller, e.g., less than about 50 nm gate length, it becomes more and more difficult to improve the short channel device performance and at the same time maintain acceptable values for off-state leakage current.
One technique for achieving this is a halo technique wherein extra dopant implant regions are formed next to the source/drain extension regions. For this prior art method to work, the junctions must be abrupt, see xe2x80x9cCMOS Devices below 0.1 nm: How High Will Performance Go?xe2x80x9d by Y. Taur, et al., pp. 1-4. In particular, for sub-50 nm devices, not only the extension regions near the channel must be abrupt, i.e., less than 4 nm/decade, but the halo profile in proximity to the extension junction must be abrupt, i.e., less than 20 nm/decade.
In the prior art, halo formation is typically carried out by a general approach wherein the halo dopants are implanted at an angle ranging from 0xc2x0 to about 70xc2x0 into the channel region. This prior art approach varies either the dose, the type of halo dopant or angle of halo implants for improving device performance.
In the article entitled xe2x80x9cHalo Doping Effects in Submicron DI-LDD Device Designxe2x80x9d by Christopher Codella, et al., pp. 230-233, there is described the optimum halo doses for improving the threshold voltage Vt and the punch-through device characteristics. Punch-through stoppers were also discussed in U.S. Pat. No. 5,320,974 to Hori, et al., which is similar to the conventional halo arrangements.
The article entitled xe2x80x9cA 0.1 nm IHLATI (Indium Halo by Large Angle Tilt Implant) MOSFET for 1.0V Low Power Applicationxe2x80x9d by Young Jin Choi, et al. describes the use of an indium halo implant and a large angle tilt for the indium halo implant which improves the short channel device characteristics of the device.
Other related articles in this field of endeavor include: xe2x80x9cHigh Carrier Velocity and Reliability of Quarter-Micron SPI (Self-Aligned Pocket Implantation) MOSFETsxe2x80x9d by A. Hori, et al. and xe2x80x9cA 0.1-xcexcm CMOS Technology with Tilt-Implanted Punch-through Stopper (TIPS)xe2x80x9d by T. Hori.
None of the above cited prior art references provides a method of improving the abruptness of the halo dopant profiles in the area next to the channel. Instead, in the prior art processes, the halo implants will suffer enhanced transient diffusion during extension junction and high thermal budget deep source/drain rapid thermal annealing (typically on the order of about 1000xc2x0 C. for about 5 seconds). Consequently, these much degraded halo implant regions severely compromise their usefulness for improving short channel device characteristics, which is especially the case for device channel widths below 50 nm. Thus, all the prior art approaches provide no means to minimize transient enhanced diffusion of the halo dopants and hence the prior art approaches are not capable of creating abrupt super-halo implants in the region next to the channel region.
Another problem with prior art approaches is that permanent spacers are typically required to be formed on the structure after junction formation, but prior to low-temperature silicidation. The permanent spacers are employed in the prior art to keep the silicide formed over the junctions away from the gate region. That is, if permanent spacers are not employed, the silicide contact may bridge onto the gate region. Hence, the silicide regions formed in the prior art are not self-aligned to the deep junction edge. Additionally, such a prior art approach may result in the junction being deactivated since the dopants solubility is lower at the silicidation temperature and the dopants can move off of substitutional lattice sites.
In view of the drawbacks mentioned hereinabove regarding prior art approaches, there is a continued need for providing a new and improved method to form low temperature silicide contacts which are self-aligned to the deep junction edges. Additionally, a method is also needed that is capable of making abrupt shallow junctions and halo implants that do not require a large post-halo thermal budget.
One object of the present invention is to provide a method of fabricating a complementary metal oxide semiconductor (CMOS) device that includes a low temperature silicide that is self-aligned to the deep junction edges present in the device.
Another object of the present invention is to provide a method wherein a low thermal budget is used in fabricating a CMOS device.
A further object of the present invention is to provide a method of fabricating a CMOS device that includes a self-aligned silicide region that is formed without the need of a second spacer.
A yet further object of the present invention is to fabricate a raised or non-raised source/drain (S/D) CMOS device, wherein all high temperature processes, such as source/drain anneals and selective epi growth, are performed prior to halo formation.
A still further object of the present invention is to provide a method of fabricating a CMOS device having abrupt junction profiles therein.
These and other objects and advantages are achieved in the present invention by utilizing a gate sidewall composite spacer, which is partially removed during device processing. The inventive method is capable of forming low temperature silicide contacts which are self-aligned to the deep junction edges, while still achieving the low thermal budget of conventional disposable spacer processes.
The inventive spacer is formed by deposition of a bilayer of a thin nitride followed by a thicker Si-containing film and subsequent patterning to form sidewall spacers. The source/drain regions defined by the sidewall spacer are then formed via ion implantation, after which the thick Si-containing layer of the spacer is removed, leaving the thin nitride layer of the composite spacer on the structure. The nitride layer is thereafter etched so as to form L-shaped nitride spacer on the structure. Source/drain extension regions and halo implant regions are formed by implanting through the thin horizontal elemental of the L-shaped nitride spacers. Subsequently, this allows for the formation of silicide contacts that are self-aligned to the source/drain junction, without the need for deposition of a second, non-self aligned spacer.
The inventive method thus allows for the fabrication of a raised or non-raised S/D CMOS device with all high temperature processes such as source/drain anneals and selective epi growth occurring prior to halo formation. Moreover, the inventive method provides a manner to align the subsequent silicide contact away from the shallow junction. The method of the present invention also eliminates the need to form any separate permanent spacer. Other disposable spacer schemes known to the inventors do not have a built-in method to align the silicide contact after halo formation. Moreover, the prior art schemes require a permanent spacer which does not permit self-alignment of the silicide contact and junction edges.
One aspect of the present invention thus relates to a CMOS device which includes an L-shaped nitride spacer formed on each vertical gate sidewall. Specifically, the inventive CMOS device comprises:
a plurality of patterned gate stack regions formed on a surface of a semiconductor substrate, wherein said plurality of patterned gate stack regions each includes an L-shaped nitride spacer formed on exposed vertical sidewalls thereof, said L-shaped nitride spacer having a vertical element and a horizontal element, said horizontal element is formed on a portion of said substrate that abuts the patterned gate stack region; and
silicide contacts formed on other portions of said semiconductor substrate between adjacent patterned gate stack regions not containing said horizontal element of said L-shaped nitride spacer, said silicide contacts being self-aligned to deep junction edges formed in said semiconductor substrate.
In one embodiment of the present invention, the silicide contacts are formed on a selective epitaxial Si layer that is grown on the surface of the semiconductor substrate.
Another aspect of the present invention relates to a method of forming the aforementioned CMOS device. Specifically, the inventive method comprises the steps of:
(a) providing a plurality of patterned gate stack regions on a surface of a semiconductor substrate, wherein each of said patterned gate stack regions includes exposed vertical sidewalls;
(b) forming a composite spacer on each exposed vertical sidewall, said composite spacer including a bilayer comprising a nitride layer and a Si-containing film, wherein said Si-containing film is thicker than said nitride layer and is formed on said nitride layer;
(c) forming deep source and drain regions in said surface of said semiconductor substrate;
(d) removing said Si-containing film and forming shallow junctions in said semiconductor substrate in areas abutting each of said patterned gate stack regions;
(e) removing portions of said nitride layer so as to form an L-shaped nitride spacer on each vertical sidewall of said patterned gate stack regions and activating said source and drain regions; and
(f) forming silicide contacts in exposed regions of said semiconductor substrate not containing said L-shaped nitride spacer.
In one embodiment of the present invention, a selective epi Si layer is formed on exposed regions of the semiconductor substrate, after junction formation, but prior to performing step (f). This embodiment of the present invention forms raised source/drain areas in the CMOS device.
In another embodiment of the present invention, halo and source/drain extension regions are formed in the substrate after formation of the source/drain regions, but prior to forming the silicide contact.